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234980275
Improved performance of on-chip data interconnects
Item #:
234980275
CVE 10571
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- Trading off the reliability, crosstalk delay and power dissipation on on-chip buses are challenging issue for the design community in Deep Sub Micron (DSM) and very deep beneath Micron Technologies (VDSM). To improve the overall system performance it is necessary to reduce and scaling technology to control these effects data on-chip interconnects. Error Correcting Codes (ECC) have been used on the data buses to increase the reliability of the data transfer on the bus on-chip data with penalty of overhead power, delay and area. The dynamic power dissipation of interconnects depends on supply voltage, operating clock frequency, load capacitance and switching activity. All the parameters which influence the dynamic power dissipation are technology dependent except switching activity. Dynamic power dissipation has been reduced by reducing the switching activity. The switching activity has been reduced by adopting a data encoding technique on data interconnects. Encoding the data on it interconnects the promising technique to decrease the dynamic power dissipation and total on-chip delay on the buses and hence overall system performance can be increased.
| Publisher | LAP LAMBERT Academic Publishing |
| Publication date | 20 Jun. 2020 |
| Language | English |
| Print length | 156 pages |
| ISBN-10 | 620267248X |
| ISBN-13 | 978-6202672481 |
| Item weight | 236 g |
| Dimensions | 15.01 x 0.91 x 22 cm |
Product Description
Improved performance of on-chip data interconnects
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Electronics Engineering Editorial Review
Improved Performance Of On-chip Data Interconnects is a comprehensive publication by LAP LAMBERT Academic Publishing that delves into enhancing data interconnects on chips. Spanning 156 pages, this book provides valuable insights into improving on-chip data communication, making it a compelling choice for professionals in the field. The book is presented in English and published on June 20, 2020, offering a well-researched analysis of the subject matter. It's designed for readers interested in understanding the technicalities that contribute to performance improvements in semiconductor technology.
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Pros
- Comprehensive research on on-chip data interconnects
- Published by a reputable academic publisher
- Detailed analysis spanning 156 pages
- Written in English for accessibility
- Compact dimensions for easy handling
Cons
- The publication might be too technical for casual readers
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